Vad är random access memory definition graphics
Random-access memory
Form of computer uppgifter storage
"RAM" redirects here. For other uses, see Ram.
Not to be confused with Random tillgång Memories or Random-access machine.
Random-access memory (RAM; ) fryst vatten a struktur of electronic computer memory that can be read and changed in any beställning, typically used to store working uppgifter and machine code.[1][2] A random-access memory device allows information items to be read or written in almost the same amount of time irrespective of the physical location of information inre the memory, in contrast with other direct-access information storage media (such as hard disks and magnetic tape), where the time required to read and write uppgifter items varies significantly depending on their physical locations on the recording medium, due to mechanical limitations such as media cirkelrörelse speeds and ledd movement.
In today's technology, random-access memory takes the form eller gestalt of integrated circuit (IC) chips with MOS (metal–oxide–semiconductor) memory cells. RAM fryst vatten normally associated with volatile types of memory where stored upplysning fryst vatten lost if power fryst vatten removed. The two main types of volatile random-access semiconductor memory are static random-access memory (SRAM) and dynamic random-access memory (DRAM).
Non-volatile RAM has also been developed[3] and other types of non-volatile memories allow random tillgång for read operations, but either do not allow write operations or have other kinds of limitations. These include most types of ROM and NOR flash memory.
The use of semiconductor RAM dates back to when IBM introduced the monolithic (single-chip) bit SP95 SRAM chip for their System/ Model 95 computer, and Toshiba used bipolar DRAM memory cells for its bit Toscal BC electronic calculator, both based on bipolar transistors. While it offered higher speeds than magnetic-core memory, bipolar DRAM could not compete with the lower price of the then-dominant magnetic-core memory.[4] In , Dr. Robert Dennard invented modern DRAM architecture in which there's a single MOS transistor per capacitor.[5] The first commercial DRAM IC chip, the 1K Intel , was introduced in October Synchronous dynamic random-access memory (SDRAM) was reintroduced with the Samsung KM48SL chip in
History
Early computers used relays, mechanical counters[6] or delay lines for main memory functions. Ultrasonic delay lines were serial devices which could only reproduce uppgifter in the beställning it was written. Drum memory could be expanded at relatively low cost but efficient retrieval of memory items requires knowledge of the physical layout of the drum to optimize speed. Latches built out of triode vacuum tubes, and later, out of discrete transistors, were used for smaller and faster memories such as registers. Such registers were relatively large and too costly to use for large amounts of data; generally only a few dozen or few hundred bits of such memory could be provided.
The first practical form eller gestalt of random-access memory was the Williams tube. It stored uppgifter as electrically charged spots on the face of a cathode-ray tube. Since the electron stråle of the CRT could read and write the spots on the tube in any beställning, memory was random tillgång. The capacity of the Williams tube was a few hundred to around a thousand bits, but it was much smaller, faster, and more power-efficient than using individual vacuum tube latches. Developed at the University of Manchester in England, the Williams tube provided the medium on which the first electronically stored schema was implemented in the Manchester Baby computer, which first successfully ran a schema on 21 June, [7] In fact, rather than the Williams tube memory being designed for the Baby, the Baby was a testbed to demonstrate the reliability of the memory.[8][9]
Magnetic-core memory was invented in and developed up until the mids. It became a widespread form eller gestalt of random-access memory, relying on an array of magnetized rings. bygd changing the sense of each ring's magnetization, information could be stored with one bit stored per fingerprydnad. Since every fingerprydnad had a combination of address wires to select and read or write it, tillgång to any memory location in any sequence was possible. Magnetic core memory was the standard form eller gestalt of computer memory until displaced bygd semiconductor memory in integrated circuits (ICs) during the early s.[10]
Prior to the development of integrated read-only memory (ROM) circuits, permanent (or read-only) random-access memory was often constructed using diode matrices driven bygd address decoders, or specially wound core rope memory planes.[citation needed]
Semiconductor memory appeared in the s with bipolar memory, which used bipolar transistors. Although it was faster, it could not compete with the lower price of magnetic core memory.[11]
MOS RAM
In , Frosch and Derick were able to manufacture the first silicon dioxide field effect transistors at Bell Labs, the first transistors in which drain and source were adjacent at the surface.[12] Subsequently, a grupp demonstrated a working MOSFET at Bell Labs [13][14]
This led to the development of metal–oxide–semiconductor (MOS) memory bygd John Schmidt at Fairchild Semiconductor in [10][15] In addition to higher speeds, MOS semiconductor memory was cheaper and consumed less power than magnetic core memory.[10] The development of silicon-gateMOS integrated circuit (MOS IC) technology bygd Federico Faggin at Fairchild in enabled the production of MOS memory chips.[16] MOS memory overtook magnetic core memory as the dominant memory technology in the early s.[10]
Integrated bipolar static random-access memory (SRAM) was invented bygd Robert H. Norman at Fairchild Semiconductor in [17] It was followed bygd the development of MOS SRAM bygd John Schmidt at Fairchild in [10] SRAM became an alternative to magnetic-core memory, but required six MOS transistors for each bit of data.[18] Commercial use of SRAM began in , when IBM introduced the SP95 memory chip for the System/ Model [11]
Dynamic random-access memory (DRAM) allowed replacement of a 4 or 6-transistor latch circuit bygd a single transistor for each memory bit, greatly increasing memory density at the cost of volatility. uppgifter was stored in the tiny capacitance of each transistor, and had to be periodically refreshed every few milliseconds before the charge could leak away.
Toshiba's Toscal BC electronic calculator, which was introduced in ,[19][20][21] used a form eller gestalt of capacitor-bipolar DRAM, storing bit information on discrete memory cells, consisting of germanium bipolar transistors and capacitors.[20][21] While it offered higher speeds than magnetic-core memory, bipolar DRAM could not compete with the lower price of the then dominant magnetic-core memory.[22] Capacitors had also been used for earlier memory schemes, such as the drum of the Atanasoff–Berry Computer, the Williams tube and the Selectron tube.
In , Dr. Robert Dennard invented invented modern DRAM architecture for which there's a single MOS transistor per capacitor.[18] While examining the characteristics of MOS technology, he funnen it was capable of building capacitors, and that storing a charge or no charge on the MOS capacitor could företräda the 1 and 0 of a bit, while the MOS transistor could control writing the charge to the capacitor. This led to his development of a single-transistor DRAM memory cell.[18] In , Dennard filed a patent beneath IBM for a single-transistor DRAM memory fängelse, based on MOS technology.[23] The first commercial DRAM IC chip was the Intel , which was manufactured on an 8μm MOS process with a capacity of 1kbit, and was released in [10][24][25]
The earliest DRAMs were often synchronized with the centralenhet i en dator clock (clocked) and were used with early microprocessors. In the mids, DRAMs moved to the asynchronous design, but in the s returned to synchronous operation.[26][27] In Samsung released KM48SL, which had a capacity of 16Mbit.[28][29] and mass-produced in [28] The first commercial DDR SDRAM (double uppgifter rate SDRAM) memory chip was Samsung's 64Mbit DDR SDRAM chip, released in June [30]GDDR (graphics DDR) fryst vatten a form eller gestalt of DDR SGRAM (synchronous graphics RAM), which was first released bygd Samsung as a 16Mbit memory chip in [31]
Types
The two widely used forms of modern RAM are static RAM (SRAM) and dynamic RAM (DRAM). In SRAM, a bit of information fryst vatten stored using the state of a six-transistormemory fängelse, typically using six MOSFETs. This struktur of RAM fryst vatten more expensive to tillverka, but fryst vatten generally faster and requires less dynamic power than DRAM. In modern computers, SRAM fryst vatten often used as cache memory for the centralenhet i en dator. DRAM stores a bit of uppgifter using a transistor and capacitor pair (typically a MOSFET and MOS capacitor, respectively),[32] which tillsammans comprise a DRAM fängelse. The capacitor holds a high or low charge (1 or 0, respectively), and the transistor acts as a switch that lets the control circuitry on the chip read the capacitor's state of charge or change it. As this struktur of memory fryst vatten less expensive to tillverka than static RAM, it fryst vatten the predominant struktur of computer memory used in modern computers.
Both static and dynamic RAM are considered volatile, as their state fryst vatten lost or reset when power fryst vatten removed from the struktur. bygd contrast, read-only memory (ROM) stores information bygd permanently enabling or disabling selected transistors, such that the memory cannot be altered. Writable variants of ROM (such as EEPROM and NOR flash) share properties of both ROM and RAM, enabling information to persist without power and to be updated without requiring special utrustning. ECC memory (which can be either SRAM or DRAM) includes special circuitry to detect and/or correct random faults (memory errors) in the stored information, using parity bits or error correction codes.
In general, the begrepp RAM refers solely to solid-state memory devices (either DRAM or SRAM), and more specifically the main memory in most computers. In optical storage, the begrepp DVD-RAM fryst vatten somewhat of a misnomer since, it fryst vatten not random access; it behaves much like a hard disc drive if somewhat slower. Aside, unlike CD-RW or DVD-RW, DVD-RAM does not need to be erased before reuse.
Memory cell
Main article: Memory fängelse (computing)
The memory fängelse fryst vatten the fundamental building block of computer memory. The memory fängelse fryst vatten an electronic circuit that stores one bit of binary kunskap and it must be set to store a logic 1 (high voltage level) and reset to store a logic 0 (low voltage level). Its value fryst vatten maintained/stored until it fryst vatten changed bygd the set/reset process. The value in the memory fängelse can be accessed bygd reading it.
In SRAM, the memory fängelse fryst vatten a type of flip-flop circuit, usually implemented using FETs. This means that SRAM requires very low power when not being accessed, but it fryst vatten expensive and has low storage density.
A second type, DRAM, fryst vatten based around a capacitor. Charging and discharging this capacitor can store a "1" or a "0" in the fängelse. However, the charge in this capacitor slowly leaks away, and must be refreshed periodically. Because of this refresh process, DRAM uses more power, but it can achieve greater storage densities and lower enhet costs compared to SRAM.
Addressing
To be useful, memory cells must be readable and writable. Within the RAM device, multiplexing and demultiplexing circuitry fryst vatten used to select memory cells. Typically, a RAM device has a set of address lines , and for each combination of bits that may be applied to these lines, a set of memory cells are activated. Due to this addressing, RAM devices virtually always have a memory capacity that fryst vatten a power of two.
Usually several memory cells share the same address. For example, a 4 bit 'wide' RAM chip has 4 memory cells for each address. Often the width of the memory and that of the microprocessor are different, for a 32 bit microprocessor, eight 4 bit RAM chips would be needed.
Often more addresses are needed than can be provided bygd a device. In that case, external multiplexors to the device are used to activate the correct device that fryst vatten being accessed. RAM fryst vatten often byte addressable, although it fryst vatten also possible to man RAM that fryst vatten word-addressable.[33][34]
Memory hierarchy
Main article: Memory hierarchy
One can read and over-write information in RAM. Many computer systems have a memory hierarchy consisting of processor registers, on-dieSRAM caches, external caches, DRAM, paging systems and virtual memory or swap space on a hard drive. This entire pool of memory may be referred to as "RAM" bygd many developers, even though the various subsystems can have very different tillgång times, violating the original concept behind the random access begrepp in RAM. Even within a hierarchy level such as DRAM, the specific row, column, finansinstitut, rank, kanal, or interleave organization of the components man the tillgång time variabel, although not to the extent that tillgång time to rotating storage media or a tejp fryst vatten variabel. The overall goal of using a memory hierarchy fryst vatten to obtain the fastest possible average tillgång time while minimizing the total cost of the entire memory struktur (generally, the memory hierarchy follows the tillgång time with the fast centralenhet i en dator registers at the top and the slow hard drive at the bottom).
In many modern anställda computers, the RAM comes in an easily upgraded struktur of modules called memory modules or DRAM modules about the storlek of a few sticks of chewing gum. These can be quickly replaced should they become damaged or when changing needs demand more storage capacity. As suggested above, smaller amounts of RAM (mostly SRAM) are also integrated in the centralenhet i en dator and other ICs on the motherboard, as well as in hard-drives, CD-ROMs, and several other parts of the computer struktur.
Other uses of RAM
In addition to serving as temporary storage and working space for the operating struktur and applications, RAM fryst vatten used in numerous other ways.
Virtual memory
Main article: Virtual memory
Most modern operating systems employ a method of extending RAM capacity, known as "virtual memory". A portion of the computer's hard drive fryst vatten set aside for a paging file or a scratch partition, and the combination of physical RAM and the paging en samling dokument eller en elektronisk lagring av data struktur the system's total memory. (For example, if a computer has 2GB (3 B) of RAM and a 1GB page en samling dokument eller en elektronisk lagring av data, the operating struktur has 3GB total memory available to it.) When the struktur runs low on physical memory, it can "swap" portions of RAM to the paging en samling dokument eller en elektronisk lagring av data to man room for new information, as well as to read previously swapped data back into RAM. Excessive use of this mechanism results in thrashing and generally hampers overall struktur performance, mainly because hard drives are far slower than RAM.
RAM disk
Main article: RAM drive
Software can "partition" a portion of a computer's RAM, allowing it to act as a much faster hard drive that fryst vatten called a RAM platta. A RAM platta loses the stored information when the computer fryst vatten shut down, unless memory fryst vatten arranged to have a standby battery source, or changes to the RAM platta are written out to a nonvolatile platta. The RAM platta fryst vatten reloaded from the physical platta upon RAM platta initialization.
Shadow RAM
Sometimes, the contents of a relatively slow ROM chip are copied to read/write memory to allow for shorter tillgång times. The ROM chip fryst vatten then disabled while the initialized memory locations are switched in on the same block of addresses (often write-protected). This process, sometimes called shadowing, fryst vatten fairly common in both computers and embedded systems.
As a common example, the BIOS in typical anställda computers often has an option called "use shadow BIOS" or similar. When enabled, functions that rely on uppgifter from the BIOS's ROM instead use DRAM locations (most can also toggle shadowing of film card ROM or other ROM sections). Depending on the struktur, this may not result in increased performance, and may cause incompatibilities. For example, some hardware may be inaccessible to the operating struktur if shadow RAM fryst vatten used. On some systems the benefit may be hypothetical because the BIOS fryst vatten not used after booting in favor of direkt hardware tillgång. Free memory fryst vatten reduced bygd the storlek of the shadowed ROMs.[35]
Memory wall
The 'memory wall fryst vatten the growing disparity of speed between centralenhet i en dator and the response time of memory (known as memory latency) outside the centralenhet i en dator chip. An important reason for this disparity fryst vatten the limited communication bandwidth beyond chip boundaries, which fryst vatten also referred to as bandwidth wall. From to , centralenhet i en dator speed improved at an annual rate of 55% while off-chip memory response time only improved at 10%. Given these trends, it was expected that memory latency would become an overwhelming bottleneck in computer performance.[36]
Another reason for the disparity fryst vatten the enormous increase in the storlek of memory since the uppstart of the PC revolution in the s. Originally, PCs contained less than 1 mebibyte of RAM, which often had a response time of 1 centralenhet i en dator clock cycle, meaning that it required 0 wait states. Larger memory units are inherently slower than smaller ones of the same type, simply because it takes längre for signals to traverse a larger circuit. Constructing a memory enhet of many gibibytes with a response time of one clock cycle fryst vatten difficult or impossible. Today's CPUs often still have a mebibyte of 0 wait state cache memory, but it resides on the same chip as the centralenhet i en dator cores due to the bandwidth limitations of chip-to-chip communication. It must also be constructed from static RAM, which fryst vatten far more expensive than the dynamic RAM used for larger memories. Static RAM also consumes far more power.
CPU speed improvements slowed significantly partly due to major physical barriers and partly because current centralenhet i en dator designs have already hit the memory vägg in some sense. Intel summarized these causes in a document.[37]
First of all, as chip geometries shrink and clock frequencies rise, the transistor leakage current increases, leading to excess power consumption and heat Secondly, the advantages of higher clock speeds are in part negated bygd memory latency, since memory tillgång times have not been able to keep pace with increasing clock frequencies. Third, for certain applications, traditional serial architectures are becoming less efficient as processors get faster (due to the so-called von Neumann bottleneck), further undercutting any gains that frequency increases might otherwise buy. In addition, partly due to limitations in the means of producing inductance within solid state devices, resistance-capacitance (RC) delays in meddelande transmission are growing as feature sizes shrink, imposing an additional bottleneck that frequency increases don't address.
The RC delays in meddelande transmission were also noted in "Clock Rate versus IPC: The End of the Road for Conventional Microarchitectures"[38] which projected a maximum of % average annual centralenhet i en dator performance improvement between and
A different concept fryst vatten the processor-memory performance gap, which can be addressed bygd 3D integrated circuits that reduce the distance between the logic and memory aspects that are further apart in a 2D chip.[39] Memory subsystem design requires a focus on the gap, which fryst vatten widening over time.[40] The main method of bridging the gap fryst vatten the use of caches; small amounts of high-speed memory that houses recent operations and instructions nearby the processor, speeding up the execution of those operations or instructions in cases where they are called upon frequently. Multiple levels of caching have been developed to deal with the widening gap, and the performance of high-speed modern computers relies on evolving caching techniques.[41] There can be up to a 53% difference between the growth in speed of processor and the lagging speed of main memory access.[42]
Solid-state hard drives have continued to increase in speed, from ~Mbit/s via SATA3 in up to ~7GB/s via NVMe/PCIe in , closing the gap between RAM and hard platta speeds, although RAM continues to be an beställning of magnitude faster, with single-lane DDR5 MHz capable of GB/s, and modern GDDR even faster. Fast, cheap, non-volatile solid state drives have replaced some functions formerly performed bygd RAM, such as holding certain information for immediate availability in dator farms - 1 terabyte of SSD storage can be had for $, while 1TB of RAM would cost thousands of dollars.[43][44]
Timeline
See also: Flash memory §Timeline, Read-only memory §Timeline, and Transistor count §Memory
SRAM
| Date of introduction | Chip name | Capacity (bits) | Access time | SRAM type | Manufacturer(s) | Process | MOSFET | Ref |
|---|---|---|---|---|---|---|---|---|
| March | — | 1 | ? | Bipolar (cell) | Fairchild | — | — | [11] |
| ? | 8 | ? | Bipolar | IBM | ? | — | ||
| SP95 | 16 | ? | Bipolar | IBM | ? | — | [45] | |
| ? | 64 | ? | MOSFET | Fairchild | ? | PMOS | [46] | |
| TMC | 16 | ? | Bipolar (TTL) | Transitron | ? | — | [10] | |
| ? | ? | ? | MOSFET | NEC | ? | ? | [47] | |
| ? | 64 | ? | MOSFET | Fairchild | ? | PMOS | [47] | |
| ? | MOSFET | NEC | ? | NMOS | ||||
| ? | MOSFET | IBM | ? | NMOS | [46] | |||
| ? | ? | Bipolar | IBM | ? | — | [11] | ||
| ns | MOSFET | Intel | 12, nm | PMOS | [48][49][50][51] | |||
| 1 kbit | ? | MOSFET | Intel | ? | NMOS | [48] | ||
| 1 kbit | ns | MOSFET | Intel | ? | CMOS | [48][52] | ||
| A | 1 kbit | ns | MOSFET | Intel | ? | NMOS (depletion) | [48][53] | |
| 4 kbit | ns | MOSFET | Intel | ? | NMOS | [48][52] | ||
| 1 kbit | 70 ns | MOSFET | Intel | ? | NMOS (HMOS) | [48][49] | ||
| 4 kbit | 55 ns | MOSFET | Intel | ? | NMOS (HMOS) | [48][54] | ||
| ? | 4 kbit | ? | MOSFET | Toshiba | ? | CMOS | [49] | |
| HM | 4 kbit | 55 ns | MOSFET | Hitachi | 3, nm | CMOS (twin-well) | [54] | |
| TMS | 16 kbit | ? | MOSFET | Texas Instruments | ? | NMOS | [49] | |
| ? | 16 kbit | ? | MOSFET | Hitachi, Toshiba | ? | CMOS | [55] | |
| 64 kbit | ? | MOSFET | Matsushita | |||||
| ? | 16 kbit | ? | MOSFET | Texas Instruments | 2,nm | NMOS | [55] | |
| October | ? | 4 kbit | 18 ns | MOSFET | Matsushita, Toshiba | 2,nm | CMOS | [56] |
| ? | 64 kbit | ? | MOSFET | Intel | 1, nm | NMOS (HMOS) | [55] | |
| February | ? | 64 kbit | 50 ns | MOSFET | Mitsubishi | ? | CMOS | [57] |
| ? | kbit | ? | MOSFET | Toshiba | 1,nm | CMOS | [55][50] | |
| ? | 1 Mbit | ? | MOSFET | Sony, Hitachi, Mitsubishi, Toshiba | ? | CMOS | [55] | |
| December | ? | kbit | 10 ns | BiMOS | Texas Instruments | nm | BiCMOS | [58] |
| ? | 4 Mbit | 15–23 ns | MOSFET | NEC, Toshiba, Hitachi, Mitsubishi | ? | CMOS | [55] | |
| ? | 16 Mbit | 12–15 ns | MOSFET | Fujitsu, NEC | nm | |||
| December | ? | kbit | ns | MOSFET | IBM | ? | CMOS (SOI) | [59] |
| ? | 4 Mbit | 6 ns | Cache (SyncBurst) | Hitachi | nm | CMOS | [60] | |
| Mbit | ? | MOSFET | Hyundai | ? | CMOS | [61] |
DRAM
| Date of introduction | Chip name | Capacity (bits) | DRAM type | Manufacturer(s) | Process | MOSFET | Area | Ref |
|---|---|---|---|---|---|---|---|---|
| — | 1 bit | DRAM (cell) | Toshiba | — | — | — | [20][21] | |
| — | 1 bit | DRAM (cell) | IBM | — | MOS | — | [23][47] | |
| ? | bit | DRAM (IC) | Fairchild | ? | PMOS | ? | [10] | |
| — | 1 bit | DRAM (cell) | Intel | — | PMOS | — | [47] | |
| 1 kbit | DRAM (IC) | Intel, Honeywell | ? | PMOS | ? | [47] | ||
| 1 kbit | DRAM | Intel | 8, nm | PMOS | 10mm2 | [62][63][24] | ||
| μPD | 1 kbit | DRAM | NEC | ? | NMOS | ? | [64] | |
| ? | 2 kbit | DRAM | General Instrument | ? | PMOS | 13mm2 | [65] | |
| 4 kbit | DRAM | Intel | ? | NMOS | ? | [48][66] | ||
| ? | 8 kbit | DRAM | IBM | ? | PMOS | 19mm2 | [65] | |
| 16 kbit | DRAM | Intel | ? | NMOS | ? | [67][10] | ||
| ? | 64 kbit | DRAM | NTT | ? | NMOS | 35mm2 | [65] | |
| MK | 16 kbit | PSRAM | Mostek | ? | NMOS | ? | [68] | |
| ? | 64 kbit | DRAM | Siemens | ? | VMOS | 25mm2 | [65] | |
| ? | kbit | DRAM | NEC, NTT | 1,–1, nm | NMOS | 34–42mm2 | [65] | |
| ? | kbit | DRAM | IBM | ? | MOS | 25mm2 | [69] | |
| ? | 64 kbit | DRAM | Intel | 1, nm | CMOS | 20mm2 | [65] | |
| kbit | DRAM | NTT | ? | CMOS | 31mm2 | |||
| January 5, | ? | 8 Mbit | DRAM | Hitachi | ? | MOS | ? | [70][71] |
| February | ? | 1 Mbit | DRAM | Hitachi, NEC | 1, nm | NMOS | 74–76mm2 | [65][72] |
| NTT | nm | CMOS | 53mm2 | [65][72] | ||||
| TMS | 64 kbit | DPRAM (VRAM) | Texas Instruments | ? | NMOS | ? | [73][74] | |
| January | μPD | kbit | DPRAM (VRAM) | NEC | ? | NMOS | ? | [75][76] |
| June | ? | 1 Mbit | PSRAM | Toshiba | ? | CMOS | ? | [77] |
| ? | 4 Mbit | DRAM | NEC | nm | NMOS | 99mm2 | [65] | |
| Texas Instruments, Toshiba | 1,nm | CMOS | –mm2 | |||||
| ? | 16 Mbit | DRAM | NTT | nm | CMOS | mm2 | [65] | |
| October | ? | kbit | HSDRAM | IBM | 1,nm | CMOS | 78mm2 | [78] |
| ? | 64 Mbit | DRAM | Matsushita, Mitsubishi, Fujitsu, Toshiba | nm | CMOS | ? | [55] | |
| ? | Mbit | DRAM | Hitachi, NEC | nm | CMOS | ? | ||
| ? | 4 Mbit | DPRAM (VRAM) | Hitachi | ? | CMOS | ? | [60] | |
| January 9, | ? | 1 Gbit | DRAM | NEC | nm | CMOS | ? | [79][60] |
| Hitachi | nm | CMOS | ? | |||||
| ? | 4 Mbit | FRAM | Samsung | ? | NMOS | ? | [80] | |
| ? | 4 Gbit | QLC | NEC | nm | CMOS | ? | [55] | |
| ? | 4 Gbit | DRAM | Hyundai | ? | CMOS | ? | [61] | |
| June | TC51WXB | 32 Mbit | PSRAM | Toshiba | ? | CMOS | ? | [81] |
| February | ? | 4 Gbit | DRAM | Samsung | nm | CMOS | ? | [55][82] |
SDRAM
Part of this section fryst vatten transcluded from Synchronous dynamic random-access memory. (edit history)